Senior Principal Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary: We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.

Qualifications:

• BE/BTech/ME/MS/MTech

Job Responsibilities:

Experience: 15+yrs

• Candidate must be able to generate RTL/handle scalable designs up to 48 billion Gates. Should be able to modify/update the designs to stress Flip-Flops/Wires/Gates/Input Outputs.
• Should be able use various available scalable compile/Runtime flows for large scalable designs. Should be able to profile and identify the slow performance areas and work with R&D on enhancements.
• Should be proficient in Verilog/ System-Verilog, scripting and exposure to Emulation platform is a must.

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