The Senior Engineer I - DFT will lead DFT strategy, develop verification methodologies, automate test bench creation, and ensure timing checks for SoCs.

The role involves driving backend processes, optimizing design for power and area, and ensuring timing closure and physical verification for IC design.

Develop Interface and Analog IPs for ASIC and external customers, ensuring solid IP development methodologies and supporting multiple customers through hands-on engineering.

Develop device interface functions, oversee firmware lifecycle, collaborate on validation requirements, mentor junior engineers, and enhance processes.

You will develop methodologies and flows for DFT in a collaborative environment, creating verification solutions, timing checks, and implementing automated verification techniques.

You will architect and develop IP blocks for CXL/PCIE ASICs/FPGA, lead projects, streamline processes, and manage team development.