The Senior Engineer I - DFT will lead DFT strategy, develop verification methodologies, automate test bench creation, and ensure timing checks for SoCs.

Develop Interface and Analog IPs for ASIC and external customers, ensuring solid IP development methodologies and supporting multiple customers through hands-on engineering.

This role involves driving backend physical design processes, including power planning, timing verification, and physical verification for IC design.

Develop device interface functions, oversee firmware lifecycle, collaborate on validation requirements, mentor junior engineers, and enhance processes.

Responsible for verifying IP, Block, or Subsystem at SoC level. Duties include developing verification environments, documentation, and debugging tasks.

The role involves managing a design/RTL team, supporting pre-sales architecture proposals, and ensuring delivery of micro-architecture for SoCs. Responsibilities include collaboration with customers, IP vendors, and technical support.

Responsible for pre-sales support, architecture proposal, managing design teams, achieving project goals, and providing technical support to customers.

The Design Verification Engineer will oversee verification of new features, build testbenches, and integrate protocols while collaborating with various technical teams to improve methodologies.

You will develop methodologies and flows for DFT in a collaborative environment, creating verification solutions, timing checks, and implementing automated verification techniques.

Responsible for verification of IP or SoC level components, analyzing and debugging verification tasks, and developing verification environments.

Lead the design and development of IP blocks for ASIC/FPGA projects, manage teams, and streamline projects using advanced methodologies and tools.

You will architect and develop IP blocks for CXL/PCIE ASICs/FPGA, lead projects, streamline processes, and manage team development.