The Senior Engineer II Analog Design role involves developing Interface and Analog IPs for ASIC or external clients, focusing on Hard Analog or PHY block circuit design at advanced technology nodes. The engineer will drive IP development processes and support multiple customer projects, utilizing comprehensive knowledge of the ASIC and IP development lifecycle.

As a Senior Engineer I in Physical Design at Alphawave Semi, you will drive backend processes, including floor-planning, low-power design, place and route optimization, clock tree synthesis, and static timing verification. Your role will focus on ensuring design integrity through physical verification and power integrity signoff while working collaboratively with a dynamic team.

The Senior Engineer I - Software role involves developing and validating firmware for UCIe chiplets, collaborating with various design teams, mentoring junior engineers, and overseeing firmware lifecycle from design to post-silicon optimization.

Responsible for the verification of IP, Block, or Subsystem at SoC Level, generating documentation for verification, analyzing/debugging blocks in verification, and developing verification environments and components. Reports to the Lead Engineer.

The Senior Staff Engineer I - RTL Design will lead pre-sales support, develop architectures, manage the design/RTL team, ensure project delivery, and collaborate with customers and IP vendors to enhance design processes and methodologies.

The role involves pre-sales support, proposing and managing architecture for customers, overseeing the design team, ensuring project goals are achieved, and enhancing methodologies for improved workflow. Responsibilities also include collaborating with IP vendors and providing technical support to customers.

The Design Verification Engineer will own the verification of new customer features, review specifications, build testbenches, analyze test failures, facilitate RTL design and MATLAB model bit-matching, and support post-silicon validation. The role requires collaboration with various teams and contributions towards improving verification methodologies.

The Engineer II - DFT will lead the development of DFT methodologies for integrated designs and collaborate on automation and verification test benches. Responsibilities include architecting DFT environments, managing a team, and ensuring quality implementation through timing checks and verification standards.

The Principal Engineer - SOC Verification is responsible for the verification of IP, Block, or Subsystem at the SoC level, creating documentation, debugging, and developing the verification environment and components. The role requires extensive knowledge of digital verification techniques and protocols, and collaboration within a hybrid work setup.

The Senior Staff Engineer I will lead ASIC or FPGA projects, deliver standards-compliant IP blocks, streamline development processes, and manage staffing and employee development. The role requires expertise in Verilog, System Verilog, and experience with various verification and scripting methodologies.