The Design Engineer II will be responsible for RTL design and integration, collaborating with architects and verification teams to ensure design quality through checks and adherence to release protocols.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
Selected Candidate is responsible for RTL Design & Integration. Need to work closely with Architects and Verification team.
Responsible to achieve required design quality by doing Lint and CDC checks and adhering to release checklists.
Skillset/ Requirements:
- BTech/ MTech in Engineering with 3 to 6 years of actual work experience in RTL Design.
- The ideal candidate should have thorough understanding of end-to-end Digital design flow.
- Verilog / System-Verilog RTL logic design, debug, and functional verification support.
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of Lint checks and proper resolution of errors
- Working experience on APB and AXI protocols.
- Working experience on micro-controller based designs and its associated logic is a Strong plus.
- Experience in Digital microarchitecture definition and documentation is a plus
- Experience in synthesis timing constraints, static timing analysis and constraint development is a plus
- Experience with FPGA and/or emulation platform is a plus.
- Exhibit excellent communication skills and be self-motivated and well organized.
Top Skills
Apb
Axi
Cdc Checks
Digital Design Flow
Fpga
Lint Checks
Rtl Design
System-Verilog
Verilog
Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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