The role involves design verification of hardware and software safety mechanisms, leading a team, and developing functional safety work products.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
BE/BTECH/ME/MTECH Or Equivalent Degree
EXP7-13years
Design Verification role for IP development team.
- Position is based in Bangalore, part of Cadence IP Group.
Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) - UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
- In addition to UVM functional verification, role could involve Formal verification of complex design modules.
- In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
- Understand design and produce detailed verification strategy and test plan.
Self-starter and learner with passion for getting the job done on time with great quality. - Strong problem solving, analytical and debug skills
- Excellent verbal and written communications skills
Top Skills
Assembly Language
C
C++
Eda Simulation
Iso 26262
Perl
Systemverilog
Unix
Verilog
Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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