Position: Principal Software Engineer
Location: Bangalore
Job Description
Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence’s Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product.
Job Responsibilities:
The role’s day to day responsibilities cover:
R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power.
This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!
Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.
Job Qualifications:
BE/BTech/ME/MTech- Computer Science or others
Experience: 7-10 Years
Required Skills
The successful candidate will possess the following combination of education and experience:
Proficient in C/C++
Excellent programming and software engineering skills
Experience with UNIX and/or LINUX platforms is preferred
RTL knowledge – System Verilog, VHDL is preferred
Strong knowledge of Tcl is preferred
Experience in language compiler
Prior experience with large software development projects is highly recommended
Prior experience with timing analysis software development projects is highly recommended
Data structure and algorithmic skills
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Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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