The Sr Principal Design Engineer will be responsible for RTL design and development for DDR Memory Controller IP, including working with existing RTL, adding new features, verification regressions, and ensuring compliance with design guidelines. The role involves significant interaction with customers and supporting their configurations.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Description:
- RTL Design Engineer for DDR Memory Controller IP development team.
- The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
- The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.
Position Requirements:
- BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
- RTL Design using Verilog is a must.
- System Verilog experience and experience with UVM based environment usage / debugging is required.
- AXI3/4 experience is desired.
- DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
- Prior experience in IP development teams would be an added advantage.
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Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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