Jobs at Broadcom

Provides advanced technical support for enterprise customers using Symantec security products. Diagnoses complex software, hardware, networking, infrastructure, operating system, and security issues; manages cases and customer expectations; collaborates with product, engineering, sales, and vendors; documents solutions; identifies bugs; supports testing and product improvements; and mentors or trains other support engineers.

Provides advanced technical support for enterprise customers using Symantec security products. Diagnoses complex software, hardware, networking, infrastructure, operating system, and security issues; manages cases and customer expectations; documents resolutions; collaborates with engineering, product, sales, and vendors; identifies bugs; supports testing and product improvements; creates technical documentation; and mentors or trains support personnel. The role operates in a shift model and requires strong troubleshooting, networking, Windows infrastructure, security, and customer-facing communication skills.

Perform SoC DFT architecture, test insertion and verification, ATPG and pattern generation, coverage improvement, vector simulation, post-silicon debug, and yield improvement. Collaborate with Physical Design and STA teams on DFT timing closure, work with globally distributed teams, interact with customers, and independently resolve complex technical issues. Strong DFT expertise and debugging skills are required; scripting and Tessent Shell experience are advantageous.

Lead SoC DFT activities including architecture, test insertion and verification, ATPG pattern generation, coverage improvement, vector simulation, post-silicon debug, and yield improvement. Collaborate with physical design and STA teams on DFT timing closure, support customer interactions, and work independently across global teams. Strong DFT expertise, debugging skills, communication, and scripting experience are required.

Develop and execute pre-silicon ASIC verification using emulation platforms. Create chip-level tests, synthesizable Verilog/SystemVerilog models, automation scripts, and reusable verification components. Debug hardware and software issues, optimize emulation methodologies, and collaborate with architecture, design, design verification, and firmware teams to achieve coverage goals.

Develop verification test plans, functional coverage, reusable SystemVerilog and UVM testbenches, BFMs, checkers, monitors, scoreboards, and pseudo-random tests for ASIC IP, subsystems, and SoCs. Debug RTL and gate-level regression failures, analyze coverage gaps, improve tests, and document verification strategies. The role requires independent work across flexible project assignments.

Leads static timing analysis and signoff for block- and full-chip semiconductor designs across modes, corners, and process variations. Develops and validates SDC constraints, analyzes setup, hold, clock, signal integrity, and low-power timing issues, and drives ECO-based timing closure through tapeout. Collaborates with synthesis, CTS, physical design, RTL, and signoff teams while producing reports and communicating convergence status.

Leads physical design implementation for complex SoCs on 5nm and sub-5nm nodes, owning floorplanning, placement, CTS, routing, extraction, timing closure, ECOs, physical verification, and GDSII signoff. Develops and optimizes automation flows, resolves complex design issues, improves turnaround time and quality, and mentors a distributed physical design team. Collaborates across engineering functions and global sites to deliver production-ready silicon.