The Principle Design Engineer at Cadence will work on cutting-edge technology, applying their expertise in electronic design to deliver software and hardware solutions. They will be responsible for using various Cadence tools, conducting design and verification, and solving technical challenges while collaborating with a diverse team.

The Lead Design Engineer at Cadence is responsible for digital design implementation, PPA optimization of advanced IP cores, and automation of EDA flows using various Cadence tools. The role involves managing regression infrastructure and participating in benchmarking customer engagements.

The Functional Safety Engineer will implement ISO 26262 safety plans for automotive software tools and libraries at Cadence, collaborating with various safety organizations and internal teams to ensure compliance and improve processes. Responsibilities include creating safety documentation, supporting safety work products, reviewing safety standards, and providing training.

The Lead Design Engineer at Cadence is responsible for ASIC design and verification, particularly in the PCIe and storage domains. The role requires strong debugging skills and effective communication to tackle complex technological challenges.

The Lead Design Engineer at Cadence will develop performance models, conduct architectural tradeoff analysis, and facilitate data-driven design for DDR memory controller architectures. Responsibilities include modeling in SystemC or C++, correlating performance data, collaborating with architects, analyzing various architectural scenarios, and automating performance metrics generation post-simulation.

The Sr Principal Design Engineer will be responsible for RTL design and development for DDR Memory Controller IP, including working with existing RTL, adding new features, verification regressions, and ensuring compliance with design guidelines. The role involves significant interaction with customers and supporting their configurations.

As a Principal Design Engineer at Cadence, you will design, develop, and maintain software in areas such as gcc/llvm toolchains and standard libraries. The role involves testing new hardware features, collaborating with teams to resolve complex issues, and maintaining documentation.

The Principal Design Engineer will develop performance models for DDR memory controller architectures, conduct architectural tradeoff analyses, and create scripts for performance metrics automation. The role requires strong hardware modeling and coding expertise in C++ and SystemC, alongside a solid understanding of computer architecture and performance principles.

As a Principal Design Engineer, you will develop and verify hardware and software safety mechanisms for Xtensa processors, implementing test benches, diagnostics, and coverage monitors, while collaborating with various teams and contributing to functional safety documentation for certification.

The Lead Design Engineer will be a key member of the DDR controller team, overseeing activities related to DDR controller IP, including customer engagement, pre-silicon integration, and post-silicon support.

The Principle Design Engineer at Cadence will engage in designing and developing electronic systems utilizing their experience with Ethernet Controllers, MIPI, and various AMBA protocols. The role involves collaborating with a diverse team to innovate within the field of electronic design.

The Principal Technical Quality Engineer will work with design teams and management to enhance processes, ensure high product quality, and represent the quality team to clients. Key tasks include defining quality procedures, maintaining quality metrics, conducting root-cause analyses, and managing quality certifications.

As an Assistant Manager in Accounts, you will manage the Royalty Analytics process, ensuring timely invoicing and reporting. You will prepare quarterly Royalty Income accrual data and reconcile reports with actuals. Additionally, you'll play a key role in the accounting team, manage auditing processes, and ensure compliance with statutory requirements in India.

As a Principal Design Engineer at Cadence, you will lead the design verification team responsible for hardware and software safety mechanisms of Xtensa processors. Your role includes implementing test benches, conducting fault simulations, and providing essential documentation for product safety certification in the automotive safety sector.

As a Design Engineer I at Cadence, you will develop and verify hardware and software safety mechanisms for Xtensa processors. Responsibilities include implementing simulation/test benches, developing functional safety work products, and collaborating with various teams to meet safety and verification goals.