Lead the digital design implementation of Cadence IPs, optimize performance and power characteristics, and automate EDA flows with various tools.

The Lead Design Engineer will develop verification plans, validate protocols, and manage defects, supporting the deep neural accelerator product line.

Develop performance models, perform architectural tradeoff analysis, and enable data-driven design decisions for DDR memory controller architectures.

The Principal Design Engineer leads the Functional Safety Design Verification Team, developing and verifying safety mechanisms in hardware and software for Xtensa processors, while ensuring compliance with safety standards.

The Lead Design Engineer will focus on ASIC design and verification, specifically in PCIe and storage technologies, requiring good debug and communication skills.

The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.