Teams at Lattice Semiconductor

Develops and validates analog, digital, and mixed-signal circuit models for FPGA products. The role uses Verilog, VHDL, SystemVerilog, SPICE, and SystemC for simulation and analysis, optimizes model accuracy and performance, collaborates with design and architecture teams, documents results, and provides technical leadership and mentorship.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.