Teams at Microsoft

Lead full-chip and package integration for DPU ASICs from early planning through tapeout signoff. Drive die/floorplanning, C4/microbump and RDL optimization, power domain management, vendor collaboration, integration milestones, and resolve power/integration issues across teams.

Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.

Lead pre-sales and technical delivery for Microsoft Industry Solutions, mapping customer needs to Microsoft Cloud and AI solutions. Drive project planning, risk mitigation, stakeholder engagement, IP reuse, and business development while mentoring teams and ensuring operational compliance.