ASIC Engineer

This unique role offers the opportunity to be part of a highly dynamic team driving flows, methodologies, and physical implementation at block level & chip level. Leveraging a strong foundation in back‑end design fundamentals and physical implementation flows, you will own block‑level implementation, support in top level floor planning, place and route, clock and power distribution, timing closure, and physical verification.

• Assist in RTL/netlist‑to‑GDSII implementation for block‑level and full‑chip designs in advanced technology nodes.
• Support digital implementation flows and collaborate with EDA tool vendors to debug issues.
• Support in developing hierarchical floor plans, macro placement, I/O planning, congestion, timing, and power distribution.
• Perform static timing analysis (STA), analyze timing reports, and implement timing ECOs using tools such as Tempus and Tempus ECO, or equivalent industry‑standard tools.
• Collaborate with RTL, Analog, DFT, Packaging, CAD, and EDA teams to resolve implementation issues and improve overall design convergence.
• Run and debug back‑end signoff checks, including power integrity, IR/EM analysis, and physical verification.
• Develop automation scripts using TCL, Python, Bash, or Perl for QoR tracking, reporting, and flow efficiency.

As a Physical Design Engineer, you will work with a diverse team of engineers across digital design, analog/mixed-signal design, DFT, verification, package engineering, CAD, and post-silicon validation. During the concept and planning phases, you will help define implementation strategy, physical constraints, and floor planning methodology. During execution, you will own block-level implementation and contribute to full-chip integration of various IPs

You will collaborate with cross-functional teams dispersed in various geo-locations to achieve timing, power, area, congestion, and signoff closure and help ensure successful silicon delivery through production.

• Bachelor’s degree in Electrical Engineering or related field (Master’s preferred) 
• 8-12 years of PD experience in ASIC/SoC physical design and implementation
• Hands-on experience with full physical design flow including floor planning, power planning, place and route, clock tree synthesis, extraction, STA, ECOs, and physical signoff
• Experience with industry‑standard synthesis tools such as Cadence Genus or equivalent; Place and Route tools like Cadence Innovus; Static Timing Analysis (STA) tools like Cadence Tempus and/or Synopsys PrimeTime; Back‑End Reliability & Power Integrity flows using tools such as Cadence Voltus or Ansys RedHawk; experience with industry‑standard physical verification tools such as Siemens Calibre and/or Cadence Pegasus.
• Strong scripting skills in TCL, Python, or Perl for automation and flow development
• Familiarity with ASIC/SoC design flow, DFT concepts, and Linux-based development environments
• You must be a team player and be able to collaborate effectively.
• Strong analytical, problem-solving, debugging, teamwork skills.

• Bachelor’s or Master’s in Electrical Engineering or equivalent field
• 3+ years of PD experience in ASIC/SoC physical design and implementation in advanced CMOS tech nodes
• Proven hands-on experience with the full physical design flow at block and/or chip level PD
• Good understanding of various EDA tools and sign-off criteria
• Good team player

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