The Lead Design Engineer at Cadence is responsible for ASIC design and verification, particularly in the PCIe and storage domains. The role requires strong debugging skills and effective communication to tackle complex technological challenges.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.
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Top Skills
Asic
Cadence Design Systems Pune, Maharashtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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