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Cadence Design Systems

Lead Design Engineer

Reposted 21 Days Ago
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In-Office
Pune, Maharashtra
Mid level
In-Office
Pune, Maharashtra
Mid level
The Lead Design Engineer will focus on ASIC design and verification, specifically in PCIe and storage technologies, requiring good debug and communication skills.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Asic Design
Emmc
Onfi
Pcie
Sd
Xspi

Cadence Design Systems Pune, Mahārāshtra, IND Office

Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006

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