Lead Design Engineer will develop complex test benches and verification infrastructure for Deep Neural Accelerator products, requiring collaboration with team members and defect validation.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Experience in developing complex test bench in System Verilog using OVM/UVM methodology
- Experience in coding functional coverage and system verilog assertions.
- Experience validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.
- Knowledge of computer architecture, AI accelerators is a big plus.
- Well versed with System Verilog and popular EDA (Cadence Xcelium preferred) simulation, System Verilog assertions and testbench methodologies
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Excellent written and oral communication skills necessary
Job Role:
- He/She will be a part of design verification team supporting the DNA (Deep Neural Accelerator) product line.
- Work closely with the designers/micro-architect to understand the design.
- Work on complete or part of the verification plan, review the same with others in the team.
- Develop the verification infrastructure and carryout validation.
- Log/Track and validate defects.
- B.E/B.Tech 4+ years of experience in Design Verification.or M.E/M.Tech with 2+ years of experience
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Ahb
Axi4
Cadence Xcelium
Dma
Eda
Ovm
Perl
System Verilog
Unix Shell
Uvm
Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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