The Principal Design Engineer will develop performance models for DDR memory controller architectures, conduct architectural tradeoff analyses, and create scripts for performance metrics automation. The role requires strong hardware modeling and coding expertise in C++ and SystemC, alongside a solid understanding of computer architecture and performance principles.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Performance Modeling Engineer
Location – India (Pune)
Summary
We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.
Responsibilities
- Develop cycle-level performance models in SystemC or C++
- Correlate performance models to match RTL configurations and traffic conditions
- Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
- Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
- Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
- Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks
Required Skills
- BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
- 8+ years of experience in hardware modeling, functional or performance
- Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
- Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
Additional Skills
- Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
- Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
- Experience using performance simulators – Memory Controller, NoC, CPU models
- Coding in Python and familiarity with packages like Pandas, Matplotlib
- Experience working with performance benchmarks – SPEC, STREAM, etc
- Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies
We’re doing work that matters. Help us solve what others can’t.
Top Skills
C++
Python
Systemc
Cadence Design Systems Pune, Maharashtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
Similar Jobs
Automotive • Hardware • Robotics • Software • Transportation • Manufacturing
As a Senior Design Engineer at Magna, you'll work on developing automotive technologies, ensuring high-quality product delivery while being part of a dynamic and innovative team.
Legal Tech • Software
The role involves developing and supporting RTL for DDR Memory Controller IP, ensuring verification, and cleaning the design according to guidelines while adding new features and supporting customers.
Top Skills:
System VerilogVerilog
Legal Tech • Software
The Principal Design Engineer will develop performance models for DDR memory controllers, conduct architectural tradeoff analysis, and support data-driven design decisions. Responsibilities include developing cycle-level performance models, analyzing trade-offs, and automating performance metrics generation through scripting.
Top Skills:
C++PythonSystemc
What you need to know about the Pune Tech Scene
Once a far-out concept, AI is now a tangible force reshaping industries and economies worldwide. While its adoption will automate some roles, AI has created more jobs than it has displaced, with an expected 97 million new roles to be created in the coming years. This is especially true in cities like Pune, which is emerging as a hub for companies eager to leverage this technology to develop solutions that simplify and improve lives in sectors such as education, healthcare, finance, e-commerce and more.
