Jobs at Lattice Semiconductor

Lead cross-functional FPGA silicon, Soft-IP and software tool programs. Manage scope, schedule, risks, resources, and stakeholder alignment across global teams to ensure timely, high-quality product delivery and executive reporting.

Design, develop, and maintain FPGA software tools and infrastructure; implement features for next-generation FPGA products; support existing tools; produce functional specifications and unit test plans; review marketing requirements; improve development methodologies and collaborate across teams.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Maintain and optimize custom layout CAD flows using Cadence Virtuoso and related EDA tools. Develop automation (SKILL, Python, Tcl, Perl) for handoffs, PDK enablement, libraries, and CI pipelines. Debug tool/flow issues, evaluate EDA quality, collaborate with design and foundry teams, mentor engineers, and support global CAD infrastructure including version control and compute farm tools.

Develop and improve FPGA place-and-route software tools focusing on Isolation Design Flow and QoR (performance, area, runtime, memory). Implement new features, support new FPGA products, write unit tests, collaborate cross-functionally, and support customer needs.

Provide legal support for global operations including subsidiary governance, cross-border employment and HR matters, compliance, managing outside counsel, post-acquisition integration, and building legal processes, templates, and playbooks. Advise business leaders and collaborate with HR, Finance, Tax, and other teams to enable scalable, compliant multinational operations.

Develop and improve FPGA place-and-route engines and related EDA tools, optimize QoR (performance, area, runtime, memory), support new FPGA products, implement features, create unit tests, and collaborate cross-functionally to support customers and maintain tool quality.

Lead block-level physical implementation of digital blocks/IP from netlist to GDSII: floorplanning, power planning, placement, CTS, routing, STA, physical verification and sign-off, low-power implementation (UPF), flow automation, ECO support, and tape-out correlation.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.

Lead and operate HPC cluster management (LSF), administer public and private clouds, manage display solutions (ETX/VNC/EOD), hardware revision control and release tools, and oversee compute, storage, licensing, archive, disaster recovery and remote desktop systems. Drive GenAI application and automation initiatives, adopt best practices, collaborate globally, mentor colleagues, and travel occasionally.

Lead development and validation of analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use SPICE and HDL simulations (Verilog/VHDL/SystemVerilog), mentor modeling engineers, collaborate with design teams, analyze simulation results, optimize models for performance and accuracy, and document modeling processes.

Lead firmware architecture and technical strategy for Edge AI systems. Drive complex design and integration, mentor engineers, collaborate with hardware/software/product teams, ensure system-level scalability, reliability and performance, and participate in code reviews and software development.

Develop, validate, and optimize analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use Verilog/VHDL/SystemVerilog and SPICE simulations, analyze results, collaborate with design teams, mentor engineers, and document modeling processes.

Senior individual contributor defining a multi-year edge AI vision and driving hardware-aware model architectures, compiler/ML co-design, and extreme-efficiency techniques across Lattice FPGAs and partner NPUs. Lead ambiguous cross-functional initiatives, build R&D prototypes and model zoo, mentor senior engineers, and align ML strategy with hardware roadmaps and business goals.

Lead IP and full-chip FPGA/SoC subsystem design and integration, define micro-architecture, drive logic design to meet performance/power/area targets, conduct reviews/audits, collaborate across functions and global teams, and mentor engineering members.

Lead development of FPGA place-and-route engines and advanced security flows (e.g., Isolation Design Flow). Optimize QoR (performance, area, runtime, memory), support new FPGA products, implement features, write unit tests, collaborate cross-functionally, and support customers.

Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog. Drive logic design, enforce coding standards, run quality checks (lint, CDC, RDC, SDC), develop assertions/checkers, collaborate with architects and global teams, mentor engineers, and support FPGA full-chip integration and debug.

Senior R&D role on the Architecture modelling team to define, develop, debug and troubleshoot complex SystemC and firmware models. Lead and mentor engineers in a model-first design flow, improve development methodologies, drive projects, and coordinate cross-functional teams.