Jobs at Lattice Semiconductor

Designs and develops embedded reference applications for ARM and RISC-V microcontrollers. Responsibilities include hardware, FPGA, and silicon bring-up; embedded software development in C, C++, and Python; RTOS integration; board support and device drivers; build systems, automated testing, and CI; debugging; customer support; technical documentation; code reviews; and mentoring junior engineers.

Own full-cycle talent acquisition for specialized semiconductor and FPGA engineering roles, initially supporting India and later global sourcing needs. Develop passive-candidate sourcing strategies using Boolean, X-ray, headhunting, technical communities, referrals, and AI/ML tools. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and build global engineering talent pipelines.

Owns architecture, design, validation, bring-up, and production release of high-speed FPGA-based boards. Responsibilities include hardware specifications, schematics, BOMs, signal and power integrity, thermal analysis, component engineering, layout collaboration, debugging, documentation, and cross-functional delivery. The role leads design reviews, mentors engineers, works with suppliers and manufacturing partners, and drives board-development methodology improvements.

Leads the creation and scaling of Lattice’s datacenter module solutions team in Pune. Owns end-to-end productization of BMC, M.2, DC-SCM, and MCM-based solutions from concept through production. Establishes technical strategy, architecture, integration, validation, quality processes, and roadmaps while collaborating with hardware, firmware, QA, product, sales, and customers. Recruits and mentors engineering talent, promotes responsible generative AI adoption, and reports program health and risks to executive leadership.

Owns and advances FPGA CAD/EDA methodologies for static timing analysis, timing abstraction, place and route, physical implementation, signoff, and design QA. Develops automated EDA flows, supports advanced-node designs, drives timing and physical closure, validates ETM/QTM models, resolves tool and technology issues, mentors engineers, and aligns methodology across global design teams.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog. Drive logic design, enforce coding standards, run quality checks (lint, CDC, RDC, SDC), develop assertions/checkers, collaborate with architects and global teams, mentor engineers, and support FPGA full-chip integration and debug.

Leads firmware architecture, technical strategy, complex design and integration across projects. Mentors engineers, collaborates with hardware, software, and product teams, participates in code reviews, and ensures firmware scalability, reliability, and performance. Requires extensive embedded systems experience, C/C++ expertise, RTOS knowledge, hardware-software co-design experience, and system-level performance optimization skills.

Leads the Pune firmware organization responsible for architecture, development, integration, validation, security, release, and lifecycle management of multiple firmware stacks. Establishes secure development and compliance processes, drives pre- and post-silicon bring-up, collaborates with ASIC, FPGA, verification, security, and product teams, and partners with customers and infrastructure vendors. Recruits and develops engineering talent, reports program status to executives, and applies generative AI to improve engineering productivity.

Develop and architect Lattice’s FPGA EDA toolchain, including synthesis, place and route, and timing analysis. Collaborate across engineering teams to deliver a standards-compliant, reliable, and high-performance tool suite. Translate marketing requirements into technical specifications, own specification and planning processes, improve development methodologies, and lead projects and technical discussions.

Drive cross-functional FPGA silicon, Soft-IP, hardware, and software programs through architecture, design, verification, validation, qualification, and release. Manage scope, schedules, resources, risks, reporting, requirements, dependencies, and issue resolution while aligning global engineering, operations, marketing, and executive stakeholders. Translate product requirements into execution plans and ensure timely, high-quality delivery.

Leads cross-functional delivery of datacenter, AI infrastructure, rack management, and platform solutions from concept through deployment and production. Owns program planning, dependencies, risks, executive visibility, customer escalations, lifecycle governance, release readiness, and portfolio execution. Partners with hyperscalers, OEMs, ODMs, and engineering teams to define requirements, resolve system-level challenges, and shape future solution roadmaps.

Architects firmware solutions for Edge AI, drives technical strategy, leads complex design and integration across projects, mentors engineers, collaborates with hardware and software teams, conducts code reviews, and ensures system scalability, reliability, and performance. The role requires extensive embedded firmware experience, strong C/C++ and RTOS expertise, hardware-software co-design experience, and technical leadership.

Develop and maintain large-scale FPGA EDA software and infrastructure using C++. Build capabilities for next-generation FPGA products, support existing design tools, improve development processes, and contribute to specifications and testing. The role focuses on advanced security flows, including isolation design and partial reconfiguration, while requiring cross-functional collaboration and technical leadership.

Design Verification Engineer responsible for verifying complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, infrastructure, coverage-driven tests, and subsystem environments. Verify IP using protocols such as AMBA, PCI Express, Ethernet, and USB, while supporting low-power, boot-up, power-cycling, and hardware-software interaction verification. Collaborate with design, architecture, software, firmware, and IP teams to improve quality and tape-out readiness.

Develops and validates analog, digital, and mixed-signal circuit models for FPGA products. The role uses Verilog, VHDL, SystemVerilog, SPICE, and SystemC for simulation and analysis, optimizes model accuracy and performance, collaborates with design and architecture teams, documents results, and provides technical leadership and mentorship.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Manage the full lifecycle of EDA and enterprise software vendor engagements, including contracts, renewals, licensing, purchase requisitions, purchase orders, budgets, legal reviews, negotiations, and audits. Coordinate hundreds of concurrent workstreams across engineering, finance, legal, procurement, and global vendors. Track license utilization, costs, deadlines, compliance, and documentation while identifying optimization opportunities and reporting vendor performance to management.

Lead AI strategy and development focused on RAG, code generation, agentic AI, LLM fine-tuning, and AI-assisted software engineering. Build scalable retrieval pipelines, AI search and chatbot tools, automated test-generation systems, and cloud-based MLOps infrastructure. Integrate AI capabilities into IDE and CI/CD workflows, optimize real-time inference, mentor 3–5 AI engineers, and establish secure, reliable, and bias-aware AI development practices.

Perform pre- and post-layout signal and power integrity simulations, including IR drop, impedance, EMC, crosstalk, jitter, and eye-diagram analysis. Develop modeling methodologies, package and system integration guidelines, and design recommendations for advanced packaging. Use simulation and lab data to troubleshoot failures, determine root causes, optimize package and SI designs, and collaborate with package design and testing teams.