Jobs at Lattice Semiconductor

Leads the Pune firmware organization responsible for architecture, development, integration, validation, security, release, and lifecycle management of multiple firmware stacks. Establishes secure development and compliance processes, drives pre- and post-silicon bring-up, collaborates with ASIC, FPGA, verification, security, and product teams, and partners with customers and infrastructure vendors. Recruits and develops engineering talent, reports program status to executives, and applies generative AI to improve engineering productivity.

Develop and architect Lattice’s FPGA EDA toolchain, including synthesis, place and route, and timing analysis. Collaborate across engineering teams to deliver a standards-compliant, reliable, and high-performance tool suite. Translate marketing requirements into technical specifications, own specification and planning processes, improve development methodologies, and lead projects and technical discussions.

Drive cross-functional FPGA silicon, Soft-IP, hardware, and software programs through architecture, design, verification, validation, qualification, and release. Manage scope, schedules, resources, risks, reporting, requirements, dependencies, and issue resolution while aligning global engineering, operations, marketing, and executive stakeholders. Translate product requirements into execution plans and ensure timely, high-quality delivery.

Leads cross-functional delivery of datacenter, AI infrastructure, rack management, and platform solutions from concept through deployment and production. Owns program planning, dependencies, risks, executive visibility, customer escalations, lifecycle governance, release readiness, and portfolio execution. Partners with hyperscalers, OEMs, ODMs, and engineering teams to define requirements, resolve system-level challenges, and shape future solution roadmaps.

Architects firmware solutions for Edge AI, drives technical strategy, leads complex design and integration across projects, mentors engineers, collaborates with hardware and software teams, conducts code reviews, and ensures system scalability, reliability, and performance. The role requires extensive embedded firmware experience, strong C/C++ and RTOS expertise, hardware-software co-design experience, and technical leadership.

Develop and maintain large-scale FPGA EDA software and infrastructure using C++. Build capabilities for next-generation FPGA products, support existing design tools, improve development processes, and contribute to specifications and testing. The role focuses on advanced security flows, including isolation design and partial reconfiguration, while requiring cross-functional collaboration and technical leadership.

Design Verification Engineer responsible for verifying complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, infrastructure, coverage-driven tests, and subsystem environments. Verify IP using protocols such as AMBA, PCI Express, Ethernet, and USB, while supporting low-power, boot-up, power-cycling, and hardware-software interaction verification. Collaborate with design, architecture, software, firmware, and IP teams to improve quality and tape-out readiness.

Develops and validates analog, digital, and mixed-signal circuit models for FPGA products. The role uses Verilog, VHDL, SystemVerilog, SPICE, and SystemC for simulation and analysis, optimizes model accuracy and performance, collaborates with design and architecture teams, documents results, and provides technical leadership and mentorship.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Manage the full lifecycle of EDA and enterprise software vendor engagements, including contracts, renewals, licensing, purchase requisitions, purchase orders, budgets, legal reviews, negotiations, and audits. Coordinate hundreds of concurrent workstreams across engineering, finance, legal, procurement, and global vendors. Track license utilization, costs, deadlines, compliance, and documentation while identifying optimization opportunities and reporting vendor performance to management.

Lead AI strategy and development focused on RAG, code generation, agentic AI, LLM fine-tuning, and AI-assisted software engineering. Build scalable retrieval pipelines, AI search and chatbot tools, automated test-generation systems, and cloud-based MLOps infrastructure. Integrate AI capabilities into IDE and CI/CD workflows, optimize real-time inference, mentor 3–5 AI engineers, and establish secure, reliable, and bias-aware AI development practices.

Designs functional and automated tests for ASIC, SoC, firmware, hardware, and software solutions. Builds automation frameworks, validates hardware-firmware integration, performs performance benchmarking, investigates defects, and verifies fixes. Collaborates with hardware, firmware, and product teams, translates customer workflows into test scenarios, improves testing efficiency, reports product quality, and mentors junior QA engineers.

Perform pre- and post-layout signal and power integrity simulations, including IR drop, impedance, EMC, crosstalk, jitter, and eye-diagram analysis. Develop modeling methodologies, package and system integration guidelines, and design recommendations for advanced packaging. Use simulation and lab data to troubleshoot failures, determine root causes, optimize package and SI designs, and collaborate with package design and testing teams.

Lead design verification for complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, test cases, and coverage-driven methodologies. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and firmware interactions, and support low-power, boot-up, power-cycling, and accelerated-platform verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Own end-to-end talent acquisition for specialized semiconductor engineering roles, initially in India and later supporting global and US sourcing. Develop proactive sourcing strategies for passive technical candidates using Boolean, X-ray, AI/ML, and unconventional channels. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and collaborate on global talent strategies. The role requires deep semiconductor recruiting expertise, strong business acumen, and executive-level communication.

Verify complex FPGA and SoC designs from concept through tape-out using SystemVerilog, UVM, reusable testbenches, coverage-driven testing, and verification plans. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and high-speed protocols, and support low-power, boot-up, power-cycling, and hardware/firmware interaction verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Leads hands-on hardware and firmware QA engineering, including end-to-end functional, integration, system, black-box, grey-box, and non-functional testing. Develops test plans, automation frameworks, scripts, quality gates, and acceptance criteria; performs debugging and root cause analysis. Manages and mentors a QA team, coordinates workloads, reports quality metrics and risks, and drives process improvements. The role also requires developing AI tools for test-case creation and orchestrated test execution.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.