Jobs at Lattice Semiconductor

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Manage the full lifecycle of EDA and enterprise software vendor engagements, including contracts, renewals, licensing, purchase requisitions, purchase orders, budgets, legal reviews, negotiations, and audits. Coordinate hundreds of concurrent workstreams across engineering, finance, legal, procurement, and global vendors. Track license utilization, costs, deadlines, compliance, and documentation while identifying optimization opportunities and reporting vendor performance to management.

Lead AI strategy and development focused on RAG, code generation, agentic AI, LLM fine-tuning, and AI-assisted software engineering. Build scalable retrieval pipelines, AI search and chatbot tools, automated test-generation systems, and cloud-based MLOps infrastructure. Integrate AI capabilities into IDE and CI/CD workflows, optimize real-time inference, mentor 3–5 AI engineers, and establish secure, reliable, and bias-aware AI development practices.

Designs functional and automated tests for ASIC, SoC, firmware, hardware, and software solutions. Builds automation frameworks, validates hardware-firmware integration, performs performance benchmarking, investigates defects, and verifies fixes. Collaborates with hardware, firmware, and product teams, translates customer workflows into test scenarios, improves testing efficiency, reports product quality, and mentors junior QA engineers.

Perform pre- and post-layout signal and power integrity simulations, including IR drop, impedance, EMC, crosstalk, jitter, and eye-diagram analysis. Develop modeling methodologies, package and system integration guidelines, and design recommendations for advanced packaging. Use simulation and lab data to troubleshoot failures, determine root causes, optimize package and SI designs, and collaborate with package design and testing teams.

Lead design verification for complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, test cases, and coverage-driven methodologies. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and firmware interactions, and support low-power, boot-up, power-cycling, and accelerated-platform verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Own end-to-end talent acquisition for specialized semiconductor engineering roles, initially in India and later supporting global and US sourcing. Develop proactive sourcing strategies for passive technical candidates using Boolean, X-ray, AI/ML, and unconventional channels. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and collaborate on global talent strategies. The role requires deep semiconductor recruiting expertise, strong business acumen, and executive-level communication.

Verify complex FPGA and SoC designs from concept through tape-out using SystemVerilog, UVM, reusable testbenches, coverage-driven testing, and verification plans. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and high-speed protocols, and support low-power, boot-up, power-cycling, and hardware/firmware interaction verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Leads hands-on hardware and firmware QA engineering, including end-to-end functional, integration, system, black-box, grey-box, and non-functional testing. Develops test plans, automation frameworks, scripts, quality gates, and acceptance criteria; performs debugging and root cause analysis. Manages and mentors a QA team, coordinates workloads, reports quality metrics and risks, and drives process improvements. The role also requires developing AI tools for test-case creation and orchestrated test execution.

Senior individual contributor defining a multi-year edge AI vision and driving hardware-aware model architectures, compiler/ML co-design, and extreme-efficiency techniques across Lattice FPGAs and partner NPUs. Lead ambiguous cross-functional initiatives, build R&D prototypes and model zoo, mentor senior engineers, and align ML strategy with hardware roadmaps and business goals.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.

Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.

Own India statutory tax compliance (direct, indirect, TDS/TCS), manage audits and provisioning, prepare tax provisions and disclosures for ROW, review contracts for tax implications, coordinate with global tax teams, and support accounting and month-end tax activities.

Lead full-chip backend integration and RTL-to-GDSII physical design, including power and bump planning, floorplanning, EM-IR and signal EM analysis, DRC/LVS/PERC/ESD signoff, scripting for methodology, and cross-functional collaboration and mentorship to enable tapeout.

Design and develop RTL for low-power FPGA machine-learning engines, optimize datapaths for high throughput and low latency, implement ML operators (e.g., convolution), collaborate with algorithm and architecture teams, perform functional simulation and synthesis, and achieve timing closure for ML accelerators.

Lead silicon design validation: develop validation/characterization plans, create RTL test logic, perform silicon bring-up and debug, characterize IP performance, analyze statistical data, prepare datasheets, collaborate cross-functionally, and support post-release customer issues.