Jobs at Lattice Semiconductor

Perform pre- and post-layout signal and power integrity simulations, including IR drop, impedance, EMC, crosstalk, jitter, and eye-diagram analysis. Develop modeling methodologies, package and system integration guidelines, and design recommendations for advanced packaging. Use simulation and lab data to troubleshoot failures, determine root causes, optimize package and SI designs, and collaborate with package design and testing teams.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Lead design verification for complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, test cases, and coverage-driven methodologies. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and firmware interactions, and support low-power, boot-up, power-cycling, and accelerated-platform verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Own end-to-end talent acquisition for specialized semiconductor engineering roles, initially in India and later supporting global and US sourcing. Develop proactive sourcing strategies for passive technical candidates using Boolean, X-ray, AI/ML, and unconventional channels. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and collaborate on global talent strategies. The role requires deep semiconductor recruiting expertise, strong business acumen, and executive-level communication.

Verify complex FPGA and SoC designs from concept through tape-out using SystemVerilog, UVM, reusable testbenches, coverage-driven testing, and verification plans. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and high-speed protocols, and support low-power, boot-up, power-cycling, and hardware/firmware interaction verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Leads hands-on hardware and firmware QA engineering, including end-to-end functional, integration, system, black-box, grey-box, and non-functional testing. Develops test plans, automation frameworks, scripts, quality gates, and acceptance criteria; performs debugging and root cause analysis. Manages and mentors a QA team, coordinates workloads, reports quality metrics and risks, and drives process improvements. The role also requires developing AI tools for test-case creation and orchestrated test execution.

Senior individual contributor defining a multi-year edge AI vision and driving hardware-aware model architectures, compiler/ML co-design, and extreme-efficiency techniques across Lattice FPGAs and partner NPUs. Lead ambiguous cross-functional initiatives, build R&D prototypes and model zoo, mentor senior engineers, and align ML strategy with hardware roadmaps and business goals.

Design, develop, and maintain FPGA software tools and infrastructure; implement features for next-generation FPGA products; support existing tools; produce functional specifications and unit test plans; review marketing requirements; improve development methodologies and collaborate across teams.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Maintain and optimize custom layout CAD flows using Cadence Virtuoso and related EDA tools. Develop automation (SKILL, Python, Tcl, Perl) for handoffs, PDK enablement, libraries, and CI pipelines. Debug tool/flow issues, evaluate EDA quality, collaborate with design and foundry teams, mentor engineers, and support global CAD infrastructure including version control and compute farm tools.

Provide legal support for global operations including subsidiary governance, cross-border employment and HR matters, compliance, managing outside counsel, post-acquisition integration, and building legal processes, templates, and playbooks. Advise business leaders and collaborate with HR, Finance, Tax, and other teams to enable scalable, compliant multinational operations.

Develop and improve FPGA place-and-route engines and related EDA tools, optimize QoR (performance, area, runtime, memory), support new FPGA products, implement features, create unit tests, and collaborate cross-functionally to support customers and maintain tool quality.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.

Lead development and validation of analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use SPICE and HDL simulations (Verilog/VHDL/SystemVerilog), mentor modeling engineers, collaborate with design teams, analyze simulation results, optimize models for performance and accuracy, and document modeling processes.

Develop, validate, and optimize analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use Verilog/VHDL/SystemVerilog and SPICE simulations, analyze results, collaborate with design teams, mentor engineers, and document modeling processes.

Lead IP and full-chip FPGA/SoC subsystem design and integration, define micro-architecture, drive logic design to meet performance/power/area targets, conduct reviews/audits, collaborate across functions and global teams, and mentor engineering members.

Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog. Drive logic design, enforce coding standards, run quality checks (lint, CDC, RDC, SDC), develop assertions/checkers, collaborate with architects and global teams, mentor engineers, and support FPGA full-chip integration and debug.

Senior R&D role on the Architecture modelling team to define, develop, debug and troubleshoot complex SystemC and firmware models. Lead and mentor engineers in a model-first design flow, improve development methodologies, drive projects, and coordinate cross-functional teams.