Broadcom Logo

Broadcom

Physical Design Engineer

Reposted 4 Days Ago
Be an Early Applicant
In-Office
Kharadi, Pune, Maharashtra, IND
Senior level
In-Office
Kharadi, Pune, Maharashtra, IND
Senior level
Lead and execute backend SoC physical design for 5nm and below: floorplanning, partitioning, placement, CTS, routing, extraction, physical verification, timing closure, ECOs, and automation using Cadence/Synopsys/Mentor EDA tools and scripting (Tcl/Perl).
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria
for achieving Right-first time silicon.
Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning,
partitioning, placement, clock tree synthesis, route and physical verification.
Responsibilities include, but not limited to:
• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO

• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications:
MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of experience
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Broadcom Pune, Mahārāshtra, IND Office

Cluster B, Wing 2, EON Free Zone, Kharadi, Pune, Maharashtra, India, 411014

Similar Jobs

4 Days Ago
In-Office
Kharadi, Pune, Maharashtra, IND
Senior level
Senior level
Software • Semiconductor • Manufacturing
Lead SOC physical design work including block-level floorplanning, placement, CTS, routing, and physical verification. Perform STA, equivalence checks, crosstalk/noise analysis, power optimization, and implement timing/functional ECOs. Collaborate globally, guide team members, and adapt to new tools and methodologies.
Top Skills: Antenna ChecksCalibreClock Tree Synthesis (Cts)Crosstalk AnalysisDrcEco ImplementationEncounterErcFloorplanningFormal VerificationIccInnovusLecLvsPlacementPower OptimizationPrimetimeRoutingSta
4 Days Ago
In-Office
Kharadi, Pune, Maharashtra, IND
Senior level
Senior level
Software • Semiconductor • Manufacturing
Lead physical design for complex ASICs across architecture, logic, synthesis, place-and-route, timing and power analysis. Owns design delivery, mentors junior engineers, evaluates process flow and vendor capabilities, and manages major projects.
8 Days Ago
In-Office or Remote
India
Senior level
Senior level
Hardware • Semiconductor • Manufacturing
Design and verify high-speed mixed-signal communication and high-performance digital circuits. Perform RTL coding, simulation, synthesis, timing closure, verification, and debugging at circuit and behavioral levels. Prepare test methods, specifications, datasheets, and demo boards. Collaborate with analog and digital teams and manage multiple tasks to deliver projects on time.
Top Skills: Analog Ic DesignDigital Logic DesignMixed-Signal Communication CircuitsRtlSimulationSynthesisSystemverilogTiming ClosureVerilog

What you need to know about the Pune Tech Scene

Once a far-out concept, AI is now a tangible force reshaping industries and economies worldwide. While its adoption will automate some roles, AI has created more jobs than it has displaced, with an expected 97 million new roles to be created in the coming years. This is especially true in cities like Pune, which is emerging as a hub for companies eager to leverage this technology to develop solutions that simplify and improve lives in sectors such as education, healthcare, finance, e-commerce and more.

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account