N Human Resources & Management Systems
Senior Physical Design Engineer - Mumbai
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Lead full-chip and block-level physical design from floorplanning through GDSII, including placement, clock-tree synthesis, routing, timing, power, signal-integrity, IR-drop, EM, and physical verification signoff. Resolve closure issues, support advanced-node tapeouts, collaborate with CAD, methodology, and IP teams, and mentor junior engineers.
We are looking for a Senior Physical Design Engineer to join our VLSI delivery team. You will own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.
Key Responsibilities:
- Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus
- Drive STA, IR-drop/EM, and physical verification signoff
- Resolve timing, congestion and power closure issues
- Collaborate with CAD, methodology and IP teams on delivery cadence
- Mentor junior engineers
Requirements:
- 4+ years of hands-on Physical Design experience across Synthesis-to-GDSII
- Strong command of ICC2/Innovus
- Experience taking multiple chips to tapeout on advanced nodes
- Solid understanding of STA, power and signal-integrity closure
- Bachelor's/Master's in EE/ECE or related field
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