The role requires a Sr. Principal Design Engineer with extensive experience in RTL design and development, particularly using Verilog and System Verilog, to solve complex engineering challenges.
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Job Summary
We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.
Key Responsibilities
- Architect and implement RTL for PCIe IP blocks
- Collaborate with system architects to define micro-architecture and design specifications.
- Responsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.
- Work closely with verification teams to develop testbenches and validate functionality.
- Participate in interoperability testing
- Contribute to performance, power, and area optimization in advanced nodes.
- Interface with cross-functional teams including PHY, software, and validation.
Required Skills
- Strong hands-on experience in RTL design using Verilog/SystemVerilog.
- Deep understanding of PCIe protocol stack and transaction layers.
- Experience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,
- Familiarity with CDC design principles and asynchronous FIFO implementation.
- Proficiency in synthesis, linting, and static timing analysis.
- Exposure to formal verification and assertion-based design methodologies.
- Experience with simulation tools and waveform debugging.
Education
- Bachelor’s or Master’s degree in Electronics /Electrical Engineering , or related field.
Top Skills
Pcie
System Verilog
Uvm
Verilog
Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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