The Sr Principal Design Engineer will oversee the physical design process of complex Memory IPs, mentor junior engineers, and ensure design compliance with specifications.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing, and physical verification. The role also involves collaborating with cross-functional teams, mentoring junior engineers, and ensuring design meets performance, power, and area specifications.
Qualifications
- Strong expertise in floorplanning, placement, clock tree synthesis, routing, and physical verification
- Experience with physical design tools like Cadence Innovus, Synopsys ICC2, or similar
- Proficient in scripting languages such as TCL, Perl, and Python for design automation
- Knowledge of timing analysis, signal integrity, and power analysis
- Excellent problem-solving skills and attention to detail
- Strong communication and collaborative skills
- Bachelor’s or Master’s degree in Electrical Engineering or related field
- 11-15 years of relevant experience in physical design
- Experience in leading and mentoring a team
Top Skills
Cadence Innovus
Perl
Python
Synopsys Icc2
Tcl
Cadence Design Systems Pune, Mahārāshtra, IND Office
Building No 1 , First Floor, Samrat Ashok Path, Commerzone IT Park, Yerawada, Pune, Maharashtra, India, 411006
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