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Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.

Lead SoC Architect responsible for defining top-level SoC architecture, subsystem partitioning, and tradeoffs. Drive performance modeling and workload analysis, specify interfaces and microarchitecture, integrate third-party IP, collaborate across RTL/verification/physical/firmware/software teams, and support silicon bring-up, debugging, tuning and long-term roadmap planning.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.