Top Design Engineer Jobs in Pune

The role involves developing and supporting RTL for DDR Memory Controller IP, ensuring verification, and cleaning the design according to guidelines while adding new features and supporting customers.

The Principal Design Engineer will develop performance models for DDR memory controllers, conduct architectural tradeoff analysis, and support data-driven design decisions. Responsibilities include developing cycle-level performance models, analyzing trade-offs, and automating performance metrics generation through scripting.

The Lead Design Engineer will develop cycle-level performance models, analyze architectural trade-offs, and generate synthetic memory traffic for DDR memory controller architectures. Key tasks include collaborating with Memory Architects, correlating performance models with RTL configurations, and automating performance metric generation.

Design, develop, and maintain software tools and libraries, collaborate with other teams to create products and resolve customer issues, assist in testing new hardware features, and create documentation.

The Principal Design Engineer will lead the development and verification of safety mechanisms for Xtensa processors, including implementing test benches and conducting fault simulations. They will work closely with various teams to ensure product safety certification and documentation.

As a Principal Design Engineer at Cadence, you will drive the development and verification of hardware and software safety mechanisms for Xtensa processors, including implementing test benches and analyzing coverage information, and assisting with product safety certification documentation.

The Principal Design Engineer at Cadence will work on cutting-edge technology, focusing on the design and implementation of electronic systems. They will leverage their extensive experience in protocols and SOC platforms to deliver innovative solutions and contribute to team collaboration and customer success.

As a Design Engineer I at Cadence, you'll develop and verify hardware/software safety mechanisms for Xtensa processors, implementing test benches, diagnostics, and coverage monitors while analyzing fault simulations. You will collaborate with RTL, EDA, and Functional Safety teams and produce documentation for product safety certification.

The Lead Design Engineer at Cadence is responsible for ASIC design and verification, particularly in the PCIe and storage domains. The role requires strong debugging skills and effective communication to tackle complex technological challenges.

The Lead Design Engineer at Cadence will develop performance models, conduct architectural tradeoff analysis, and facilitate data-driven design for DDR memory controller architectures. Responsibilities include modeling in SystemC or C++, correlating performance data, collaborating with architects, analyzing various architectural scenarios, and automating performance metrics generation post-simulation.

The Sr Principal Design Engineer will be responsible for RTL design and development for DDR Memory Controller IP, including working with existing RTL, adding new features, verification regressions, and ensuring compliance with design guidelines. The role involves significant interaction with customers and supporting their configurations.

As a Principal Design Engineer, you will develop and verify hardware and software safety mechanisms for Xtensa processors, implementing test benches, diagnostics, and coverage monitors, while collaborating with various teams and contributing to functional safety documentation for certification.

The Principal Design Engineer will develop performance models for DDR memory controller architectures, conduct architectural tradeoff analyses, and create scripts for performance metrics automation. The role requires strong hardware modeling and coding expertise in C++ and SystemC, alongside a solid understanding of computer architecture and performance principles.

As a Principal Design Engineer at Cadence, you will design, develop, and maintain software in areas such as gcc/llvm toolchains and standard libraries. The role involves testing new hardware features, collaborating with teams to resolve complex issues, and maintaining documentation.

The Principle Design Engineer at Cadence will engage in designing and developing electronic systems utilizing their experience with Ethernet Controllers, MIPI, and various AMBA protocols. The role involves collaborating with a diverse team to innovate within the field of electronic design.

As a Principal Design Engineer at Cadence, you will lead the design verification team responsible for hardware and software safety mechanisms of Xtensa processors. Your role includes implementing test benches, conducting fault simulations, and providing essential documentation for product safety certification in the automotive safety sector.

As a Design Engineer I at Cadence, you will develop and verify hardware and software safety mechanisms for Xtensa processors. Responsibilities include implementing simulation/test benches, developing functional safety work products, and collaborating with various teams to meet safety and verification goals.