Top Design Engineer Jobs in Pune

4 Days AgoSaved
In-Office
Pune, MH
Mid level
Mid level
Healthtech • Biotech
Provide quality engineering support for new product development of hardware/software medical devices: execute design control, risk management, V&V/usability testing, develop engineering documentation, support manufacturing quality (MSA, control plans, PFMEA), and assist regulatory submissions and audits.
Top Skills: Design ControlsDesign History File (Dhf)Design Verification And Validation (V&V)FmeaIec 62304Iso 13485Iso 14971MsaRegulatory SubmissionRisk ManagementUsability Testing
4 Days AgoSaved
In-Office
Pune, MH
Entry level
Entry level
Healthtech • Biotech
Support senior quality engineers on new product development for medical device hardware/software. Assist with risk management (FMEA), design inputs/outputs, verification/validation and usability testing, test protocol development and reporting, design documentation and design history file activities, and manufacturing quality tasks such as measurement systems analysis and control plans.
19 Days AgoSaved
In-Office or Remote
Pune, MH
Mid level
Mid level
Blockchain
Build production-quality, pixel-accurate UI components and interactions in React Native; prototype in Figma with designers; own the design system and component library; improve performance, animations, and cross-platform UI architecture; define design-to-dev tooling and collaborate across design and engineering.
Top Skills: FigmaReact Native
6 Days AgoSaved
In-Office
Pune, MH
Senior level
Senior level
Greentech
Design complex PCB layouts for variable speed drives from concept to manufacture. Translate schematics and mechanical constraints into optimized high-speed, mixed-signal power electronics boards. Define stack-ups, layout rules, impedance control, EMC/thermal strategies, perform design reviews, and prepare manufacturing data while collaborating with cross-functional teams.
Top Skills: Altium DesignerCadence AllegroControlled ImpedanceDfaDfmDftDifferential PairsEmcHigh-Speed RoutingIpc StandardsPcb DesignPower IntegritySignal IntegrityThermal Management
25 Days AgoSaved
Remote
Pune, MH
Senior level
Senior level
Artificial Intelligence • Cloud • Hardware • Automation
Design, develop and integrate building management and controls for modular datacenter MEP systems. Own control architecture, PLC/HMI/SCADA programming, protocols, vendor review, FAT/SAT commissioning, troubleshooting, and mentor junior controls engineers while aligning with cybersecurity and IT requirements.
Top Skills: Allen-BradleyAsdBacnetBmsCctvControl LogicEpmsEthernet/IpFaHmiModbusOpc UaP&IdPaPidPlcScadaSiemensWld
Reposted 4 Days AgoSaved
Remote
Pune, MH
Senior level
Senior level
Software • Quantum Computing • Metaverse • Infrastructure as a Service (IaaS)
Lead verification for complex CPU/SoC IP and subsystems: define verification strategies and test plans, build verification environments, run and debug simulations/emulations, apply random-stimulus and coverage-driven techniques, and mentor engineers while improving verification methodologies and tools.
Top Skills: C++CpuEmulationPerlPythonRtlSimulationSocUvmVerilog
Reposted 4 Days AgoSaved
In-Office or Remote
Pune, MH
Senior level
Senior level
Software • Quantum Computing • Metaverse • Infrastructure as a Service (IaaS)
Lead verification of complex CPU/SoC IP: plan verification, build constrained-random UVM/SystemVerilog or C/C++ test environments, use SVA/formal tools, debug RTL (Verilog) in simulation/emulation, develop tests and coverage, and close verification gaps to meet tape-out requirements.
Top Skills: CC++DdrEmulationEthernetFormal Verification ToolsPciePerlPythonSimulationSvaSystemverilogUvmVerilog
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Reposted 4 Days AgoSaved
Remote
Pune, MH
Mid level
Mid level
Software • Quantum Computing • Metaverse • Infrastructure as a Service (IaaS)
Design and verify complex CPU/SoC IP by planning verification, building constrained-random UVM or C/C++ test environments, or using formal SVA tools. Debug RTL (Verilog) in simulation/emulation, write functional coverage, and close verification holes to meet tape-out requirements.
Top Skills: CC++EmulationFormal ToolsPerlPythonSimulationSvaSystemverilogUvmVerilog
Reposted 5 Days AgoSaved
In-Office or Remote
Pune, MH
Junior
Junior
Hardware • Semiconductor • Manufacturing
As a Design Verification Engineer, you will verify designs for analog and mixed signal electronics, develop verification strategies, and collaborate with teams throughout the development process.
Top Skills: CCadence ToolsPerlPythonShellSystem VerilogUvmVerilogVhdl
Reposted 5 Days AgoSaved
In-Office or Remote
Pune, MH
Junior
Junior
Hardware • Semiconductor • Manufacturing
As a Design Verification Engineer, you will ensure the quality of advanced RADAR products, involving verification of IP, Subsystem, and SoC designs, collaborating with cross-functional teams, and developing robust verification methodologies.
Top Skills: CCadence Tools (XceliumFormal Jg ApplicationsPerlPythonSafety Simulator)SystemverilogUvmVmanager
Reposted 7 Days AgoSaved
Remote
Pune, MH
Senior level
Senior level
Hardware • Semiconductor • Manufacturing
Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.
Top Skills: Advanced Node Processes (Below 12Nm)CEmulationFpga SimulationPythonSynopsys
Reposted 7 Days AgoSaved
Remote
Pune, MH
Senior level
Senior level
Hardware • Semiconductor • Manufacturing
Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.
Top Skills: AsicCadence XceliumGlsPythonRtlSdf AnnotationSocSynopsys Design CompilerSynopsys VcsSystemverilogTclVerilog
Reposted 8 Days AgoSaved
In-Office or Remote
Pune, MH
Senior level
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
Lead verification strategy and execution for complex digital and mixed-signal designs. Architect UVM/SystemVerilog environments, develop advanced test benches, define coverage metrics, lead debug and post-silicon validation, mentor junior engineers, and drive methodology improvements while collaborating with design teams and customers.
Top Skills: PerlPythonSystemverilogTclUvm
Reposted 15 Days AgoSaved
Remote
Pune, MH
Mid level
Mid level
Artificial Intelligence • Other • Sales • Software
As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.
Top Skills: AIConversational AiMachine LearningNatural Language Processing
Reposted 17 Days AgoSaved
In-Office or Remote
Pune, MH
Senior level
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
The Staff Engineer leads analog and mixed-signal block design, conducts design reviews, mentors junior engineers, and develops methodologies for advanced technology applications.
Top Skills: Cadence VirtuosoSpectreVerilog-A
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