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The Lead Design Engineer at Cadence is responsible for ASIC design and verification, particularly in the PCIe and storage domains. The role requires strong debugging skills and effective communication to tackle complex technological challenges.

The Lead Design Engineer at Cadence will develop performance models, conduct architectural tradeoff analysis, and facilitate data-driven design for DDR memory controller architectures. Responsibilities include modeling in SystemC or C++, correlating performance data, collaborating with architects, analyzing various architectural scenarios, and automating performance metrics generation post-simulation.

The Sr Principal Design Engineer will be responsible for RTL design and development for DDR Memory Controller IP, including working with existing RTL, adding new features, verification regressions, and ensuring compliance with design guidelines. The role involves significant interaction with customers and supporting their configurations.

As a Principal Design Engineer at Cadence, you will design, develop, and maintain software in areas such as gcc/llvm toolchains and standard libraries. The role involves testing new hardware features, collaborating with teams to resolve complex issues, and maintaining documentation.

The Principal Design Engineer will develop performance models for DDR memory controller architectures, conduct architectural tradeoff analyses, and create scripts for performance metrics automation. The role requires strong hardware modeling and coding expertise in C++ and SystemC, alongside a solid understanding of computer architecture and performance principles.

As a Principal Design Engineer, you will develop and verify hardware and software safety mechanisms for Xtensa processors, implementing test benches, diagnostics, and coverage monitors, while collaborating with various teams and contributing to functional safety documentation for certification.

The Lead Design Engineer will be a key member of the DDR controller team, overseeing activities related to DDR controller IP, including customer engagement, pre-silicon integration, and post-silicon support.