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Reposted 15 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
Lead the digital design implementation of Cadence IPs, optimize performance and power characteristics, and automate EDA flows with various tools.
Top Skills: Cadence Eda ToolsGenusInnovusPerlPythonTclTempusUnix ShellVoltus
Reposted 17 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
The Lead Design Engineer will develop verification plans, validate protocols, and manage defects, supporting the deep neural accelerator product line.
Top Skills: Ai AcceleratorsCadence XceliumOvmPerlSystem VerilogUnix ShellUvm
Reposted 21 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
Develop performance models, perform architectural tradeoff analysis, and enable data-driven design decisions for DDR memory controller architectures.
Top Skills: C++MatplotlibPandasPythonSvSystemcTlmUvmVerilog
Reposted 21 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
The Principal Design Engineer leads the Functional Safety Design Verification Team, developing and verifying safety mechanisms in hardware and software for Xtensa processors, while ensuring compliance with safety standards.
Top Skills: Assembly LanguageCEdaIso 26262PerlSystemverilogUnix ShellVerilog
Reposted 21 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
The Lead Design Engineer will focus on ASIC design and verification, specifically in PCIe and storage technologies, requiring good debug and communication skills.
Top Skills: Asic DesignEmmcOnfiPcieSdXspi
Reposted 21 Days AgoSaved
In-Office
4 Locations
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.
Top Skills: Axi3Axi4Ddr Memory ControllerRtl DesignSystem VerilogUvmVerilog
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