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Cadence Design Systems Logo
Cadence Design Systems

Lead Design Engineer

Reposted 17 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
Manage digital design implementation using Cadence EDA tools, optimize PPA of IP cores, automate EDA flows, and ensure quality regression.
Top Skills: Cadence Eda ToolsGenusInnovusPerlPythonTclTempusUnix ShellVoltus
Cadence Design Systems Logo
Cadence Design Systems

Lead Design Engineer

Reposted 18 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
Lead Design Engineer will develop complex test benches and verification infrastructure for Deep Neural Accelerator products, requiring collaboration with team members and defect validation.
Top Skills: AhbAxi4Cadence XceliumDmaEdaOvmPerlSystem VerilogUnix ShellUvm
Cadence Design Systems Logo
Cadence Design Systems

Principal Design Engineer

Reposted 22 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
As a Principal Design Engineer, you will lead functional safety design verification for Xtensa processors, developing verification environments and safety documentation to meet certification goals.
Top Skills: Assembly LanguageCPerlSystemverilogUnix ShellVerilog
Cadence Design Systems Logo
Cadence Design Systems

Principal Technical Quality Engineer

Reposted 22 Days AgoSaved
In-Office
4 Locations
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
The Principal Technical Quality Engineer will work with global teams to enhance semiconductor processes, ensuring quality in product delivery and managing defect analysis.
Top Skills: 5Why8DAnalog Ic DesignDigital Ic DesignIso26262Iso9001RcaSilicon Fabrication
Cadence Design Systems Logo
Cadence Design Systems

Principal Design Engineer

Reposted 22 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
Seeking a Principal Design Engineer for developing performance models and conducting architectural analysis for DDR memory controller architectures, with a focus on Cycle-level modeling in SystemC or C++.
Top Skills: C++PythonRtl-VerilogSvSystemcTlmUvm
Cadence Design Systems Logo
Cadence Design Systems

Lead Design Engineer

Reposted 22 Days AgoSaved
In-Office
Pune, Maharashtra, IND
Mid level
Mid level
Cloud • Hardware • Software • Semiconductor
The Lead Design Engineer will focus on ASIC design and verification, requiring expertise in specific design domains and strong debugging and communication skills.
Top Skills: Asic DesignEmmcOnfiPcieSdStorageXspi
Cadence Design Systems Logo
Cadence Design Systems

Sr Principal Design Engineer

Reposted 22 Days AgoSaved
In-Office
4 Locations
Senior level
Senior level
Cloud • Hardware • Software • Semiconductor
Design and support RTL for DDR Memory Controller, ensuring compliance with guidelines, verifying features, and assisting customers in configurations.
Top Skills: Axi3/4Ddr Memory ControllerRtl DesignSystem VerilogUvmVerilog
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