Top Tech Jobs & Startup Jobs in Pune

Develops and validates analog, digital, and mixed-signal circuit models for FPGA products. The role uses Verilog, VHDL, SystemVerilog, SPICE, and SystemC for simulation and analysis, optimizes model accuracy and performance, collaborates with design and architecture teams, documents results, and provides technical leadership and mentorship.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.

Designs and validates FPGA intellectual property using RTL design, logic simulation, compilation, timing closure, and hardware debugging. The role requires programming skills in languages such as C/C++, Perl, Tcl, or Python, plus experience with high-speed I/O protocols including PCIe, Ethernet, CPRI, and JESD204B/C. Responsibilities may also include hardware validation, soft IP packaging, example designs, and testbench development.

Manage the full lifecycle of EDA and enterprise software vendor engagements, including contracts, renewals, licensing, purchase requisitions, purchase orders, budgets, legal reviews, negotiations, and audits. Coordinate hundreds of concurrent workstreams across engineering, finance, legal, procurement, and global vendors. Track license utilization, costs, deadlines, compliance, and documentation while identifying optimization opportunities and reporting vendor performance to management.

Lead AI strategy and development focused on RAG, code generation, agentic AI, LLM fine-tuning, and AI-assisted software engineering. Build scalable retrieval pipelines, AI search and chatbot tools, automated test-generation systems, and cloud-based MLOps infrastructure. Integrate AI capabilities into IDE and CI/CD workflows, optimize real-time inference, mentor 3–5 AI engineers, and establish secure, reliable, and bias-aware AI development practices.

Designs functional and automated tests for ASIC, SoC, firmware, hardware, and software solutions. Builds automation frameworks, validates hardware-firmware integration, performs performance benchmarking, investigates defects, and verifies fixes. Collaborates with hardware, firmware, and product teams, translates customer workflows into test scenarios, improves testing efficiency, reports product quality, and mentors junior QA engineers.

Perform pre- and post-layout signal and power integrity simulations, including IR drop, impedance, EMC, crosstalk, jitter, and eye-diagram analysis. Develop modeling methodologies, package and system integration guidelines, and design recommendations for advanced packaging. Use simulation and lab data to troubleshoot failures, determine root causes, optimize package and SI designs, and collaborate with package design and testing teams.

Lead design verification for complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, test cases, and coverage-driven methodologies. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and firmware interactions, and support low-power, boot-up, power-cycling, and accelerated-platform verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.

Own end-to-end talent acquisition for specialized semiconductor engineering roles, initially in India and later supporting global and US sourcing. Develop proactive sourcing strategies for passive technical candidates using Boolean, X-ray, AI/ML, and unconventional channels. Partner with hiring managers, track recruiting metrics, advise leadership on talent markets and positioning, and collaborate on global talent strategies. The role requires deep semiconductor recruiting expertise, strong business acumen, and executive-level communication.

Verify complex FPGA and SoC designs from concept through tape-out using SystemVerilog, UVM, reusable testbenches, coverage-driven testing, and verification plans. Integrate IP-level and subsystem environments, verify AMBA-based interfaces and high-speed protocols, and support low-power, boot-up, power-cycling, and hardware/firmware interaction verification. Collaborate with architecture, design, software, firmware, and IP teams to improve quality and tape-out readiness.