Top Tech Jobs & Startup Jobs in Pune

Lead cross-functional FPGA silicon, Soft-IP and software tool programs. Manage scope, schedule, risks, resources, and stakeholder alignment across global teams to ensure timely, high-quality product delivery and executive reporting.

Design, develop, and maintain FPGA software tools and infrastructure; implement features for next-generation FPGA products; support existing tools; produce functional specifications and unit test plans; review marketing requirements; improve development methodologies and collaborate across teams.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Maintain and optimize custom layout CAD flows using Cadence Virtuoso and related EDA tools. Develop automation (SKILL, Python, Tcl, Perl) for handoffs, PDK enablement, libraries, and CI pipelines. Debug tool/flow issues, evaluate EDA quality, collaborate with design and foundry teams, mentor engineers, and support global CAD infrastructure including version control and compute farm tools.

Develop and improve FPGA place-and-route software tools focusing on Isolation Design Flow and QoR (performance, area, runtime, memory). Implement new features, support new FPGA products, write unit tests, collaborate cross-functionally, and support customer needs.

Provide legal support for global operations including subsidiary governance, cross-border employment and HR matters, compliance, managing outside counsel, post-acquisition integration, and building legal processes, templates, and playbooks. Advise business leaders and collaborate with HR, Finance, Tax, and other teams to enable scalable, compliant multinational operations.

Develop and improve FPGA place-and-route engines and related EDA tools, optimize QoR (performance, area, runtime, memory), support new FPGA products, implement features, create unit tests, and collaborate cross-functionally to support customers and maintain tool quality.

Lead block-level physical implementation of digital blocks/IP from netlist to GDSII: floorplanning, power planning, placement, CTS, routing, STA, physical verification and sign-off, low-power implementation (UPF), flow automation, ECO support, and tape-out correlation.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.

Lead and operate HPC cluster management (LSF), administer public and private clouds, manage display solutions (ETX/VNC/EOD), hardware revision control and release tools, and oversee compute, storage, licensing, archive, disaster recovery and remote desktop systems. Drive GenAI application and automation initiatives, adopt best practices, collaborate globally, mentor colleagues, and travel occasionally.