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The role involves implementing DFT and Test on intricate ASIC/SoC designs, requiring in-depth knowledge and hands-on experience in DFT/Test architecture, verification, and design methodologies.

Architect and lead DFT/Test implementation for complex IP and SoCs. Define methodologies and mentor a small team across multiple designs.

The Principal Engineer will define micro-architectures, implement RTL coding, collaborate with various teams, and mentor junior engineers in semiconductor solutions.