Lead and execute backend SoC physical design for 5nm and below: floorplanning, partitioning, placement, CTS, routing, extraction, physical verification, timing closure, ECOs, and automation using Cadence/Synopsys/Mentor EDA tools and scripting (Tcl/Perl).

Lead SOC physical design work including block-level floorplanning, placement, CTS, routing, and physical verification. Perform STA, equivalence checks, crosstalk/noise analysis, power optimization, and implement timing/functional ECOs. Collaborate globally, guide team members, and adapt to new tools and methodologies.

Lead physical design for complex ASICs across architecture, logic, synthesis, place-and-route, timing and power analysis. Owns design delivery, mentors junior engineers, evaluates process flow and vendor capabilities, and manages major projects.