Top Tech Jobs & Startup Jobs in Pune

Lead development and validation of analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use SPICE and HDL simulations (Verilog/VHDL/SystemVerilog), mentor modeling engineers, collaborate with design teams, analyze simulation results, optimize models for performance and accuracy, and document modeling processes.

Lead firmware architecture and technical strategy for Edge AI systems. Drive complex design and integration, mentor engineers, collaborate with hardware/software/product teams, ensure system-level scalability, reliability and performance, and participate in code reviews and software development.

Develop, validate, and optimize analog, digital, and mixed-signal circuit models for Lattice FPGAs. Use Verilog/VHDL/SystemVerilog and SPICE simulations, analyze results, collaborate with design teams, mentor engineers, and document modeling processes.

Senior individual contributor defining a multi-year edge AI vision and driving hardware-aware model architectures, compiler/ML co-design, and extreme-efficiency techniques across Lattice FPGAs and partner NPUs. Lead ambiguous cross-functional initiatives, build R&D prototypes and model zoo, mentor senior engineers, and align ML strategy with hardware roadmaps and business goals.

Lead IP and full-chip FPGA/SoC subsystem design and integration, define micro-architecture, drive logic design to meet performance/power/area targets, conduct reviews/audits, collaborate across functions and global teams, and mentor engineering members.

Lead development of FPGA place-and-route engines and advanced security flows (e.g., Isolation Design Flow). Optimize QoR (performance, area, runtime, memory), support new FPGA products, implement features, write unit tests, collaborate cross-functionally, and support customers.

Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog. Drive logic design, enforce coding standards, run quality checks (lint, CDC, RDC, SDC), develop assertions/checkers, collaborate with architects and global teams, mentor engineers, and support FPGA full-chip integration and debug.

Senior R&D role on the Architecture modelling team to define, develop, debug and troubleshoot complex SystemC and firmware models. Lead and mentor engineers in a model-first design flow, improve development methodologies, drive projects, and coordinate cross-functional teams.