Top Tech Jobs & Startup Jobs in Pune

Leads hands-on hardware and firmware QA engineering, including end-to-end functional, integration, system, black-box, grey-box, and non-functional testing. Develops test plans, automation frameworks, scripts, quality gates, and acceptance criteria; performs debugging and root cause analysis. Manages and mentors a QA team, coordinates workloads, reports quality metrics and risks, and drives process improvements. The role also requires developing AI tools for test-case creation and orchestrated test execution.

Design and develop high-speed, low-power custom circuits (memory, FPGA fabric) in advanced FinFET/nm CMOS processes. Perform schematic capture, SPICE simulation, margin and functional verification, layout planning, and tight pitch-matched memory layout. Collaborate on PPA and yield targets, manage full design flow including characterization, timing, compiler usage, and model generation, and drive innovation across FPGA product designs.

Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.

Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.

Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.

Own India statutory tax compliance (direct, indirect, TDS/TCS), manage audits and provisioning, prepare tax provisions and disclosures for ROW, review contracts for tax implications, coordinate with global tax teams, and support accounting and month-end tax activities.

Lead full-chip backend integration and RTL-to-GDSII physical design, including power and bump planning, floorplanning, EM-IR and signal EM analysis, DRC/LVS/PERC/ESD signoff, scripting for methodology, and cross-functional collaboration and mentorship to enable tapeout.

Design and develop RTL for low-power FPGA machine-learning engines, optimize datapaths for high throughput and low latency, implement ML operators (e.g., convolution), collaborate with algorithm and architecture teams, perform functional simulation and synthesis, and achieve timing closure for ML accelerators.

Lead silicon design validation: develop validation/characterization plans, create RTL test logic, perform silicon bring-up and debug, characterize IP performance, analyze statistical data, prepare datasheets, collaborate cross-functionally, and support post-release customer issues.