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Seeking a Principal Design Engineer for developing performance models and conducting architectural analysis for DDR memory controller architectures, with a focus on Cycle-level modeling in SystemC or C++.

The Lead Design Engineer will focus on ASIC design and verification, requiring expertise in specific design domains and strong debugging and communication skills.

Design and support RTL for DDR Memory Controller, ensuring compliance with guidelines, verifying features, and assisting customers in configurations.

Manage digital design implementation using Cadence EDA tools, optimize PPA of IP cores, automate EDA flows, and ensure quality regression.

Lead Design Engineer will develop complex test benches and verification infrastructure for Deep Neural Accelerator products, requiring collaboration with team members and defect validation.