Top Tech Jobs & Startup Jobs in Pune

Leads firmware architecture, technical strategy, complex design and integration across projects. Mentors engineers, collaborates with hardware, software, and product teams, participates in code reviews, and ensures firmware scalability, reliability, and performance. Requires extensive embedded systems experience, C/C++ expertise, RTOS knowledge, hardware-software co-design experience, and system-level performance optimization skills.

Leads the Pune firmware organization responsible for architecture, development, integration, validation, security, release, and lifecycle management of multiple firmware stacks. Establishes secure development and compliance processes, drives pre- and post-silicon bring-up, collaborates with ASIC, FPGA, verification, security, and product teams, and partners with customers and infrastructure vendors. Recruits and develops engineering talent, reports program status to executives, and applies generative AI to improve engineering productivity.

Develop and architect Lattice’s FPGA EDA toolchain, including synthesis, place and route, and timing analysis. Collaborate across engineering teams to deliver a standards-compliant, reliable, and high-performance tool suite. Translate marketing requirements into technical specifications, own specification and planning processes, improve development methodologies, and lead projects and technical discussions.

Drive cross-functional FPGA silicon, Soft-IP, hardware, and software programs through architecture, design, verification, validation, qualification, and release. Manage scope, schedules, resources, risks, reporting, requirements, dependencies, and issue resolution while aligning global engineering, operations, marketing, and executive stakeholders. Translate product requirements into execution plans and ensure timely, high-quality delivery.

Leads cross-functional delivery of datacenter, AI infrastructure, rack management, and platform solutions from concept through deployment and production. Owns program planning, dependencies, risks, executive visibility, customer escalations, lifecycle governance, release readiness, and portfolio execution. Partners with hyperscalers, OEMs, ODMs, and engineering teams to define requirements, resolve system-level challenges, and shape future solution roadmaps.

Architects firmware solutions for Edge AI, drives technical strategy, leads complex design and integration across projects, mentors engineers, collaborates with hardware and software teams, conducts code reviews, and ensures system scalability, reliability, and performance. The role requires extensive embedded firmware experience, strong C/C++ and RTOS expertise, hardware-software co-design experience, and technical leadership.

Develop and maintain large-scale FPGA EDA software and infrastructure using C++. Build capabilities for next-generation FPGA products, support existing design tools, improve development processes, and contribute to specifications and testing. The role focuses on advanced security flows, including isolation design and partial reconfiguration, while requiring cross-functional collaboration and technical leadership.

Design Verification Engineer responsible for verifying complex FPGA and SoC designs from concept through tape-out. Develop reusable UVM testbenches, verification plans, sequences, infrastructure, coverage-driven tests, and subsystem environments. Verify IP using protocols such as AMBA, PCI Express, Ethernet, and USB, while supporting low-power, boot-up, power-cycling, and hardware-software interaction verification. Collaborate with design, architecture, software, firmware, and IP teams to improve quality and tape-out readiness.

Develops and validates analog, digital, and mixed-signal circuit models for FPGA products. The role uses Verilog, VHDL, SystemVerilog, SPICE, and SystemC for simulation and analysis, optimizes model accuracy and performance, collaborates with design and architecture teams, documents results, and provides technical leadership and mentorship.

Design and integrate RTL for FPGA-based SoC projects, including IP blocks and full-chip designs. Define microarchitecture with architects, apply Verilog and SystemVerilog coding practices, and ensure quality through lint, CDC, RDC, SDC, assertions, checkers, and scripting. Collaborate globally, mentor engineers, teach design methodologies, and contribute to programmable FPGA fabric development. Occasional travel is required.