Top Tech Jobs & Startup Jobs in Pune

2 Months AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Semiconductor • Manufacturing
Lead QA/test for FPGA backend tools: create and run automated regression suites, analyze and drive fixes, prepare/excute test plans, debug in simulation and hardware, and automate testing using AI tools across distributed teams.
Top Skills: BitgenDdrEdaFpgaLattice DiamondMapPciePerlPlace And RoutePythonRadiantRtlSynplifyTclVerilogVivado
2 Months AgoSaved
In-Office
Pune, Maharashtra, IND
Expert/Leader
Expert/Leader
Semiconductor • Manufacturing
Lead modernization of legacy UI codebases (C++/Qt), define UX and UI architecture for EDA tools, mentor engineers, champion accessibility and visual design, run user research and usability testing, and ensure performance, scalability, and maintainability of UI systems.
Top Skills: Ai-Assisted Code-Transformation ToolsAsicC++Eda ToolsFpgaPythonQtShell ScriptingTcl
2 Months AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Semiconductor • Manufacturing
Design and integrate SoC/IP RTL for FPGA products using Verilog/SystemVerilog; define micro-architecture; perform SoC integration and quality checks (lint, CDC, RDC, SDC); develop assertions and checkers; mentor team members and collaborate with global teams. Occasional travel to support projects.
Top Skills: AmbaArmAxiCdcCpldEnetFpgaLintPcieRdcSdcSystemverilogVerilog
2 Months AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Semiconductor • Manufacturing
Design and develop RTL for low-power FPGA machine-learning engines, optimize datapaths for high throughput and low latency, implement ML operators (e.g., convolution), collaborate with algorithm and architecture teams, perform functional simulation and synthesis, and achieve timing closure for ML accelerators.
Top Skills: AsicCComputer ArchitectureDspFpgaFunctional SimulationImage ProcessingMemory ManagementNeural Network AcceleratorsRtlSynthesis FlowSystemcSystemverilogTiming ClosureVcs (Synopsys)VerilogXcelium (Cadence)
2 Months AgoSaved
In-Office
Pune, Maharashtra, IND
Senior level
Senior level
Semiconductor • Manufacturing
Lead silicon design validation: develop validation/characterization plans, create RTL test logic, perform silicon bring-up and debug, characterize IP performance, analyze statistical data, prepare datasheets, collaborate cross-functionally, and support post-release customer issues.
Top Skills: BertCoaxpressDdr4Ddr5DisplayportDphyDspEmulationEthernetFabricFpgaFpga Development ToolsHdmiHigh-Speed Board DesignI/OJesd204JmpLpddr4MipiMipi CsiMipi D-PhyMipi Dsi-2OscilloscopePciePcsPerlPllPmaProtocol AnalyzerProtocol ExerciserPrototypingPythonRRtlSdiSerdesSignal IntegrityUsbVerilogVhdlVna
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